Address test pattern generator for burst transfer operation of a sdram

Abstract

An address pattern generator for testing a semiconductor device, particularly, a synchronous DRAM is disclosed. The address pattern generator can switch an interleave mode and a sequential mode of address generation for a semiconductor device under test during a test process in real time and generates column addresses for the device under test by a Y address generation section alone. The address generator includes an address selector that selects and outputs from a lower Y address signal, Z address signal, and an operation mode control signal is arranged, a conversion memory that outputs certain conversion table contents is arranged, a multiplexer that selects and outputs an output from the conversion memory and the lower Y address signal in accordance with the burst length control signal. In another aspect, the address pattern generator includes a counter that loads the lower address signal from the Y address generator section for the sequential mode and loads a fixed value for the interleave mode, an exclusive OR gate that provides an output signal of the counter to an input terminal and the lower address signal from the Y address generation section to the other input terminal, and a multiplexer that selects the output signal of the counter for the sequential mode and the output signal of the exclusive OR gate for the interleave mode.