The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 10, 1998
Filed:
May. 09, 1997
William Schwarz, San Leandro, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A test circuit is provided for detection of data retention faults and cell stability faults of a memory array, such as a static random access memory (SRAM). The memory array test circuit comprises a weak write test circuit, a memory array address decoder, a microprocessor and display unit. During testing of the memory array, the weak test circuit controls the address decoder to decrease the voltage on the word lines so that it is less than the threshold voltage of the memory array transistors. The microprocessor then writes an inverted data to the memory array and then reads it. The read inverted data is sent to the display unit for comparison with a known template. By comparing the read inverted data to the template, defective memory cells can be identified.