The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 1998

Filed:

Apr. 10, 1997
Applicant:
Inventors:

Cyrus Y Tsui, Los Altos, CA (US);

Kapil Shankar, Fremont, CA (US);

Albert L Chan, Palo Alto, CA (US);

Assignee:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365182 ; 36518901 ; 36523001 ;
Abstract

A structure and a method provide a programmable logic device including a number of generic logic blocks and one or more application-specific block. Such application-specific block implements a specific function, such as a register file or a memory array. In one embodiment, the application specific block is programmable to be either one or more single-port memory array, a first-in-first-out (FIFO) memory, or a dual port memory array. In another embodiment, the application-specific block can be configured to be a register file, a number of counters, a number of timers, or a shift register. The application-specific block can be used in conjunction with programmable logic arrays for multiplexing input and output signals into and out of the application-specific block. Interconnectivity between the generic logic blocks and the application-specific blocks using a global routing resource integrates into a programmable logic device functions otherwise difficult to implement using only generic logic blocks.


Find Patent Forward Citations

Loading…