The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 1998

Filed:

Dec. 11, 1996
Applicant:
Inventors:

Mamoru Miyachi, Trusugashima, JP;

Toshiyuki Tanaka, Trusugashima, JP;

Yoshinori Kimura, Trusugashima, JP;

Hirokazu Takahashi, Trusugashima, JP;

Hitoshi Sato, Trusugashima, JP;

Atsushi Watanabe, Trusugashima, JP;

Hiroyuki Ota, Trusugashima, JP;

Isamu Akasaki, Nagoya, JP;

Hiroshi Amano, Nagoya, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438 29 ; 438 46 ; 438509 ; 438796 ; 148D / ; 148D / ;
Abstract

A process for producing a semiconductor emitting device of group III nitride semiconductor having a crystal layer (Al.sub.x Ga.sub.1-x).sub.1-y In.sub.y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1) includes; a step of forming at least one pn-junction or pin-junction and a crystal layer (Al.sub.x Ga.sub.1-x).sub.1-y In.sub.y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1) to which a group II element is added; and a step of forming electrodes on the crystal layer. The process further includes an electric-field-assisted annealing treatment in which the pn-junction or pin-junction is heated to the predetermined temperature range while forming and maintaining an electric field across the pn-junction or pin-junction for at least partial time period of the predetermined temperature range via the electrodes.


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