Matrix memory in virtual ground architecture

Abstract

A matrix memory with improved virtual ground architecture and evaluation circuit from which the informational content of two neighboring memory cells can be simultaneously read at a bit line during a read event. The memory cells with information '0' are realized, for example, by a respective field effect transistor with low threshold voltage. Every bit line provided for the readout is connected to the drain terminals of two neighboring field effect transistors in the same row. The source terminals are applied to one of two potentials that differ from one another. Depending upon which of the field effect transistors is conductive upon selection of the pertinent word line, different resultant potentials are obtained on the bit line. Such potentials are then converted in the evaluation circuit into binary signals that represent the read information.