Test ready compiler for design for test synthesis

Abstract

A computer implemented process and system for providing a test ready (TR) compiler with specific information regarding the impact of added scannable cells and resources on its mission mode design. In so doing, the TR compiler optimizes more effectively for added test resources (e.g., scannable cells and other scan routing resources) so that predetermined performance and design related constraints of the mission mode design are maintained. The TR compiler translates generic sequential cells into technology dependent non-scan cells. In the TR compiler, during replacement, scannable memory cells are used in place of these non-scan memory cells specified within the mission mode circuitry. In this way, the TR compiler is informed of the characteristics of the scannable memory cells during optimization. For test, the scannable memory cells are chained to each other to form chain chains of sequential cells. To account for chaining during compile, the TR compiler provides output driven loopback connections to simulate electrical characteristics of the chain during compile. In the above implementation, the TR compiler can efficiently provide translation of an HDL description with test implementations into a gate level netlist. With the addition of certain information regarding the test implementation (e.g., scan replacement is done and loopback connections are added), the TR compiler of the present invention can better optimize the overall layout for the addition of the test resources.