Scan segment processing within hierarchical scan architecture for design

Abstract

A system and method for architecting design for test circuitry (e.g., scan architecting) within an integrated circuit design having subdesigns (e.g., modules). The novel system environment contains a default operational mode (no user specification) and an operational mode based on user specifications; within either mode, the system recognizes and allows definition of subdesign scan chains which can be linked together alone or with other scan elements to architect complex scan chains (e.g., top level scan chains). Individual scan chains are constructed using user defined scan segments and detected inferred segments. Inferred segments are automatically detected if present within IC module designs. When integrated into larger scan chains, the user defined scan segments and the inferred scan segments are not modified during linking. The system includes specification, analysis, synthesis and reporting processes which can be used in an IC design having a hierarchical structure including modules. The specification process accesses a design database and a script file and allows a user to define scan configuration information and scan chain specifications (e.g., set scan path commands) to define portions of scan chains. Analysis reads the design database and performs architecting of scan chains based on inferred scan elements of the design and defined (e.g. specified) scan elements. During analysis, the logic within the design database is not altered and a script is generated for user modification/verification. Synthesis then implements the desired DFT circuitry by altering the design database based on the scan chains planned by analysis.