The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 1998
Filed:
Oct. 28, 1996
Applicant:
Inventor:
Robert Craig Bagley, San Jose, CA (US);
Assignee:
MTI Technology Corporation, Anaheim, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R / ;
U.S. Cl.
CPC ...
327 99 ; 327 20 ; 327144 ; 327153 ;
Abstract
A clock failure detection circuit which monitors a clock by comparing the clock to at least one delayed version of itself is provided. The original clock and the delayed version will be offset, such that an edge of one of them can clock a logic circuit to determine if the clock is at the proper level. By setting up the delay so that a clock edge is generated when the clock signal should be low, for instance, a bad output signal will be provided whenever the clock is high instead. This could be caused by the clock being stuck high, or by an irregular pulse width.