Lithographic process for device fabrication utilizing back-scattered

Abstract

The present invention is directed to a lithographic process for device fabrication. In lithographic processes for device fabrication, exposing radiation is used to delineate the image of a pattern into a layer of an energy sensitive resist material formed over a substrate. The pattern is then developed and the pattern is introduced into the underlying substrate. In the present invention, the substrate, typically a silicon wafer, is placed in a tool which utilizes electron beams as the exposing radiation. The silicon wafer has topographic alignment marks formed thereon. The alignment marks are used to orient the wafer in the tool accurately. The placement of the wafer in the tool is monitored by observing the intensity of the electron signal backscattered from the surface of the substrate. The alignment mark configuration is selected to provide a desired contrast between the intensity of the backscattered electron signal in the aligned state and the intensity of backscattered electron signal in the non-aligned state. The alignment mark dimensions that provide the desired contrast for a given intensity of incident electrons are selected by determining a relationship between backscattered electron signal contrast as a function of a dimensionless parameter that is the ratio of an alignment mark dimension (h) to the range (R) of the scattered electrons in the substrate. From this relationship, the desired backscattered electron signal contrast is selected. The value of the dimensionless parameter that corresponds to this data point is then used to determine the alignment mark dimension that will provide the desired backscattered electron signal contrast.