The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 1998
Filed:
Apr. 23, 1996
Takayuki Yoshida, Osaka, JP;
Takashi Otsuka, Osaka, JP;
Hiroaki Fujimoto, Osaka, JP;
Tadaaki Mimura, Osaka, JP;
Ichiro Yamane, Osaka, JP;
Takio Yamashita, Kyoto, JP;
Toshio Matsuki, Kyoto, JP;
Yoshiaki Kasuga, Shiga, JP;
Matsushita Electric Industrial Co., Ltd., Kadoma, JP;
Matsushita Electronics Corp., Takatsuki, JP;
Abstract
The present invention reduces crosstalk, which occurs as a result of interference between signals running in each of respective wiring layers of a first semiconductor chip and a second semiconductor chip stacked surface to surface with a small gap. The semiconductor device includes a first semiconductor chip 1 having a first electrode pad 2 and a first wiring layer 9 in the main surface, and a second semiconductor chip 5 having a second electrode pad 6 and a second wiring layer 10 in the main surface confronting the first semiconductor chip. A bump 4 is provided for electrically coupling the first electrode pad 2 and the second electrode pad 6 together. An insulation layer 8 is disposed between the main surfaces of first semiconductor chip 1 and second semiconductor chip 5. An electro-conductive layer 7 is disposed between the main confronting surfaces of the first semiconductor chip and the second semiconductor chip.