Speed coverage tool and method

Abstract

A test coverage tool determines the adequacy of a set of test vectors for a state simulator for exercising logic paths in a logic circuit design. The speed coverage tool generally compares state data from a state simulator and timing data from a timing simulator in order to validate whether a test vector covers a simulated timing path. In architecture, the speed coverage tool includes first logic configured to acquire state data from the logic circuit design that has been produced by a state simulator based upon test vectors. Second logic associated with the tool obtains timing data concerning one or more logic paths of the logic circuit design that has been produced using a timing simulator. Third logic associated with the test coverage tool is configured to determine a transition score by comparing the timing data with the state data. The score is indicative of the adequacy of a set of test vectors. Another feature of the test coverage tool involves analysis of sensitization data, or logic state information regarding internal nodes that should be set to particular logic states in order to enable particular logic paths. A sensitization score can be produced to indicate the extent to which sensitization data matches. Analysis of the sensitization data by the test coverage tool results in more accurate analysis and assessment of coverage.