The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 1998

Filed:

Jun. 07, 1996
Applicant:
Inventors:

Ronald L Taylor, Meridian, ID (US);

Larren Gene Weber, Calwell, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364488 ; 364578 ;
Abstract

A method and system for changing the connected behavior of a circuit design schematic at the time a netlist is being created by assigning instance parameters to each switch instance, the parameter having a value representing that the position of the switch is open or closed, the parameter being evaluated at the time the netlist is created to determine the position of the switch. When the netlist being created is a flat netlist, a closed switch condition is represented by printing information to the netlist file that identifies the nets being interconnected. When the netlist being created is a hierarchical netlist, the nets being interconnected are declared as 'artificial' ports, allowing these nets to be tracked through the hierarchy to instances at which the parameters are evaluated and to provide a connection between these nets, allowing the interconnection of nets to be specified at a level in the hierarchy other than that at which the switch is declared.


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