Symmetrical vertical lightly doped drain transistor and method of

Abstract

A symmetrical vertical lightly doped drain metal oxide semiconductor field effect transistor (VLDD MOSFET) is formed on a semiconductor substrate. The substrate includes a first region having a generally planar upper surface and a second region, projecting upwardly from the first region and having a generally planar upper surface, the second substrate region having opposed sidewalls generally normal to the upper surface of the first substrate region. A gate electrode is formed through an insulating film on the upper surface of the second substrate region, source/drain impurity regions are formed in the substrate on opposite sides of said gate electrode, and a channel region is formed under the gate electrode between the source/drain regions. Contours of equal ion concentration in the source/drain regions are non-Gaussian and an interface between the channel region and each source/drain region is generally linear beneath the gate electrode adjacent the opposing sidewalls of the second substrate region.