The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 1998

Filed:

May. 20, 1996
Applicant:
Inventors:

Ramnath Venkatraman, Austin, TX (US);

Elizabeth J Weitzman, Austin, TX (US);

Robert W Fiordalice, Austin, TX (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438622 ; 438626 ; 438627 ; 438629 ; 438633 ; 438638 ; 438643 ; 438660 ; 438666 ;
Abstract

An interconnect structure (10) is formed by filling a dual damascene structure (12) with conductive material. A barrier layer (13) is formed to serve as a seed layer and to prevent the out diffusion of copper. A first conductive layer (14) is formed to fill a first portion (21) of the damascene structure (12). A second conductive layer (16) is then formed to complete the filling of a second portion (22) of the damascene structure. A polishing process is then used to remove any excess material.


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Venkatraman, Ramnath. (1998). Method of forming an interconnect structure (U.S. Patent No. 5814557). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5814557

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