The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 1998

Filed:

Apr. 14, 1997
Applicant:
Inventors:

Harlan Sur, San Leandro, CA (US);

Olivier Laparra, San Jose, CA (US);

Dipankar Pramanik, Saratoga, CA (US);

Assignee:

VLSI Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H07L / ;
U.S. Cl.
CPC ...
438424 ; 438425 ; 438426 ; 438437 ; 148D / ;
Abstract

A semiconductor device isolating structure and method for forming such a structure. In one embodiment, an opening is formed through a mask layer overlying a semiconductor substrate. A trench of a desired depth is then etched into the semiconductor substrate at the area of the semiconductor substrate underlying the opening in the mask layer. The trench is then filled with a dielectric material. After an oxide planarizing process, the present invention exposes the dielectric-filled trench to an oxidizing environment. By filling the trench with dielectric material prior to the oxidization step, the present invention selectively oxidizes the semiconductor substrate at corners formed by the intersection of the sidewalls of the trench and the top surface of the semiconductor substrate. In so doing, the present invention forms smoothly rounded semiconductor substrate corners under the mask layer. Thus, the present invention eliminates the sharp upper corners associated with prior art shallow trench isolation methods.


Find Patent Forward Citations

Sur, Harlan. (1998). Silicon corner rounding in shallow trench isolation process (U.S. Patent No. 5811346). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5811346

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