The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 1998

Filed:

Jul. 14, 1997
Applicant:
Inventor:

Janmye Sung, Tauyuan, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257306 ; 257762 ; 257763 ;
Abstract

A DRAM device structure, using a stacked capacitor configuration, has been developed. The stacked capacitor structure is comprised of a lower, polysilicon storage node, a thin composite dielectric layer, and an overlying capacitor plate, comprised of a composite layer of an overlying polysilicon layer, on a thin amorphous silicon layer, contacting an N type source and drain region, in a semiconductor substrate. A bit line contact structure, comprised of a metal silicide - polysilicon composite structure, is also used in the DRAM device structure. A PFET device, adjacent to the stacked capacitor DRAM device, featuring a two part contact structure, to P type source and drain regions, comprised of a wide top, aluminum - copper shape, overlying a narrower tungsten stud, is also used in this invention.


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