The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 1998
Filed:
Feb. 13, 1997
Donald J Verhaeghe, Colorado Springs, CO (US);
William F Kraus, Colorado Springs, CO (US);
Yoshihiko Yasu, Koganei, JP;
Ramtron International Corporation, Colorado Springs, CO (US);
Hitachi, Ltd., Tokyo, JP;
Abstract
A test mode circuit for an integrated circuit includes a high voltage detector having an input for receiving a high voltage signal, a Schmitt trigger having an input coupled to the output of the high voltage detector, a latch having an input coupled to the output of the Schmitt trigger and an output for providing a test mode signal in a test operational mode, and additional control circuitry for disabling the high voltage detector and Schmitt trigger so that substantially all of the active current flow in the high voltage detector and Schmitt trigger is eliminated in a normal operational mode. The test mode circuit further includes circuitry for preventing a reset condition in the latch during the test mode until a power-down condition occurs. A glitch filter is also included, which is interposed between the output of the Schmitt trigger and the input to the latch. An integrated circuit pin is coupled to both the test mode circuit and to other circuitry on the integrated circuit not forming part of the test mode circuit.