The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 1998

Filed:

Feb. 27, 1995
Applicant:
Inventors:

Kenneth W Jones, Austin, TX (US);

Mark D Bader, Austin, TX (US);

Arthur D Kahlich, Austin, TX (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
711155 ; 711128 ; 711133 ; 711141 ; 711168 ; 36518904 ; 365 49 ;
Abstract

A multiple-way, set associative cache memory (20) allows burst read and burst write operations to occur simultaneously on different columns within a memory block during a read-modify-write operation. This is accomplished by using a write column logic (47) and a read column logic (51) to delay write column decode signals by one clock cycle from the read column decode signals. When data is being burst into and out of the cache during the read-modify-write operation, the first read cycle from the cache array (40) occurs, and one clock cycle later, the first write cycle occurs. The first write cycle occurs during the same time interval as the second read cycle. This increases the speed of a read-modify-write operation, relaxes timing constraints on the read and write operations, while reducing the power consumption of the cache.


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