Error detector for error detecting codes

Abstract

There is disclosed an acceptable error detector for error correcting block codes, in which of received syndrome vectors S for the received word vectors Y available from the syndrome generator, the m.sub.e -bit received subsyndromes S(m.sub.e) formed by the same components as those of the m.sub.e -bit representative subsyndromes <S(m.sub.e)> uniquely corresponding to the vectors of all the acceptable error pattern with error bits equal to or less than the acceptable number e is applied as addresses into the redundant subsyndrome table memory. Since the stored data specified by the input address are (m-m.sub.e)-bit redundant subsyndromes <S(m-m.sub.e)> which are supposed to appear in the remaining portion of S(=<S>) when the number of error bits is equal to or less than e, the remaining (m-m.sub.e)-bit received subsyndromes S(m-m.sub.e) derived from the received word vector Y in the syndrome generator and the (m-m.sub.e)-bit redundant subsyndrome <S(m-m.sub.e)> obtained from the redundant subsyndrome table memory are compared with each other by a coincidence detector to detect coincidence or noncoincidence therebetween. By this configuration, it is possible to detect whether the number of error bits in received word is acceptable.