The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 1998

Filed:

Sep. 19, 1996
Applicant:
Inventor:

Jerald N Hall, Scappoose, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K / ;
U.S. Cl.
CPC ...
371 226 ; 364580 ;
Abstract

A method and apparatus for the non-invasive testing of printed circuit board assemblies is described herein. In a first embodiment, an apparatus for testing circuit board assemblies includes a plurality of configuration selectors, a first plurality of ports, a first plurality of traces corresponding to the plurality of configuration selectors and coupled between the configuration selectors and the ports, and a second plurality of traces coupled to the first plurality of traces. In operation, the first plurality of ports place electrical signals of a first state on the first plurality of traces at a first time, and a second state at a second time. While each of the electrical signals are applied to the configuration selector via the first plurality of traces, the second plurality of traces receives associated output from the corresponding plurality of configuration selectors at the first time and the second time, wherein misconfigured or malfunctioning ones of the plurality of configuration selectors are identified.


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