Non-volatile memory array architecture

Abstract

A memory array includes a predetermined number of rows of PMOS Flash memory cells formed in each of a plurality of n- well regions of a semiconductor substrate, where each of the n- well regions defines a page of the memory array. In some embodiments, a plurality of bit lines define columns of the memory array, where the p+ drain of each of the memory cells in a common column are coupled to an associated one of the bit lines. In other embodiments, a plurality of sub-bit lines define columns of the memory array, where the p+ drain of each of the memory cells in a common column are coupled to an associated one of the sub-bit lines, and groups of a predetermined number of the sub-bit lines are selectively coupled to associated ones of a plurality of bit lines via pass transistors. During erasing operations a selected n- well region, within which are formed the memory cells of a selected page, is held at a first voltage, while the other n- well regions, within which are formed the memory cells of the respective un-selected pages, are held at a second voltage. The first and second voltages are different, thereby isolating the un-selected pages from erasing operations of the selected page.