The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 1998

Filed:

Jan. 31, 1996
Applicant:
Inventors:

Kenichi Harada, Tokyo, JP;

Takeshi Kuragaki, Tokyo, JP;

Osamu Ishihara, Tokyo, JP;

Kazuhiko Sato, Tokyo, JP;

Akiyoshi Kudo, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438 52 ; 438 53 ;
Abstract

A method of fabricating a thin film piezoelectric device includes preparing a semiconductor substrate having a surface; forming an etch stopping layer having an etching rate on the surface of the semiconductor substrate; forming a first semiconductor layer having an etching rate higher than the etching rate of the etch stopping layer on the etch stopping layer; forming a first electrode on a region of the first semiconductor layer; forming a piezoelectric film on the first electrode; forming a second electrode on the piezoelectric film; and etching a portion of the first semiconductor layer where the first electrode, the piezoelectric film, and the second electrode overlap, from the surface of the first semiconductor layer, selectively with respect to the etch stopping layer, thereby forming a cavity in the first semiconductor layer. Even when a compound semiconductor is employed as the substrate, the etching forming a cavity is stopped at the etch stopping layer in the direction perpendicular to the surface of the first semiconductor layer so that a cavity having a uniform depth is produced with high controllability.


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