The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 1998

Filed:

May. 19, 1997
Applicant:
Inventors:

Stephen C Horne, Austin, TX (US);

Richard K Klein, Mountain View, CA (US);

Asim A Selcuk, Cupertino, CA (US);

Nicholas John Kepler, Saratoga, CA (US);

Christopher A Spence, Sunnyvale, CA (US);

Raymond T Lee, Sunnyvale, CA (US);

John C Holst, San Jose, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ; G11C / ;
U.S. Cl.
CPC ...
365156 ; 365154 ; 36523006 ; 36518911 ; 365190 ;
Abstract

A memory device uses a reduced word line voltage during READ operations. The memory device includes a memory cell and a pass transistor for accessing the cell. The cell includes a storage node coupled to a pull-down transistor having substantially the same conductivity as the pass transistor. A drive circuit generates a reduced word line voltage to activate the pass transistor during a READ operation. The reduced word line voltage has a magnitude less than the magnitude of the bias voltage used to activate the pull-down transistor.


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Horne, Stephen. (1998). Memory device using a reduced word line voltage during read operations (U.S. Patent No. 5796651). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5796651

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