The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 1998

Filed:

Feb. 15, 1996
Applicant:
Inventors:

Takahisa Yamaha, Hamamatsu, JP;

Seiji Hirade, Hamamatsu, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
257750 ; 257751 ; 257763 ; 257637 ;
Abstract

After a MOS transistor having a gate electrode layer is formed on the surface of a semiconductor substrate, a first interlayer insulating film and a moisture blocking film are sequentially formed. After necessary contact holes are formed in the films, a first wiring layer is deposited and patterned together with the underlying blocking film, to form wiring layers for the connection to the transistor regions and a moisture blocking pattern covering the gate electrode layer. The first wiring layer includes a lowest Ti layer, Al alloy layer, and other layers. After a second interlayer insulating film is formed covering the first wiring layers, a second wiring layer is formed on the second interlayer insulating film. The second interlayer insulating film contains a spin-on-glass film which contains moisture. The wiring material layer prevents diffusion of moisture from the second interlayer insulating film to the electrode layer, and the moisture blocking film prevents the absorption and store of moisture related species (H.sub.2 O, OH.sup.-, H.sup.+) by the Ti layer of the wiring material layer.


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