Segmented non-volatile memory array having multiple sources

Abstract

An arrangement of non-volatile memory cells, such as flash memory cells which includes erase blocks which can be separately erased and which require a reduced amount of circuit area. The erase blocks each include an array of the cells arranged in rows and columns. Each cell in a row has its control gate connected to a common word line and its drain connected to a common bit line. All of the sources of one of the erase blocks are connected together by a source line structure which includes non-metallic source lines, such as doped semiconductor lines, which run generally parallel with respect to the word line and interconnect the sources of cell located in a row. The source line structure further includes at least one metallic source line which functions to interconnect the source regions of cells located in one of the erase block cell columns. The metallic source line of one of the erase blocks extends over, but is not connected to, the adjacent erase block, with the source lines of the erase blocks preferably being connected to a common source line decoder used to control the status of a selected one of the source lines so that a selected one of the erase blocks can be erased.