The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 1998
Filed:
Dec. 05, 1995
Applicant:
Inventors:
Chu-Tsao Yen, Fremont, CA (US);
Shih-Ked Lee, Fremont, CA (US);
Tong Zhang, San Jose, CA (US);
Pailu Wang, San Jose, CA (US);
Chuen-Der Lien, Los Altos, CA (US);
Assignee:
Integrated Device Technology, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438622 ; 438626 ; 438631 ; 438639 ; 438668 ; 438778 ; 438945 ;
Abstract
A method is provided for suppressing or eliminating void formation during the manufacture of integrated circuits. TEOS is deposited and etched to form recesses that assist in eliminating or suppressing void formation. The recesses may be located in an interlevel layer, or within the oxide layer just beneath the passivation layer.
Yen, Chu-Tsao. (1998). Method of topside and inter-metal oxide coating (U.S. Patent No. 5789314). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5789314
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile