The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 1998
Filed:
Dec. 27, 1995
Joseph F Rohlman, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A buffer comprises a memory array, a write circuit and a read circuit. The memory array comprises one or more memory banks. Each of the memory banks is made up of a plurality of memory cells. Each memory cell has one read port and one write port. The write circuit stores a first variable number of data items to the one or more memory banks by utilizing the one write port of a portion of the memory cells. The read circuit reads a second variable number of data outputs from the one or more memory banks by utilizing the one read port of a portion of the memory cells. At least of portion of the plurality of memory cells may include one or more additional write ports which are not used for writing the first variable number of data inputs to the one or more memory banks, and at least of portion of the plurality of memory cells may include one or more additional read ports which are not used for reading the second variable number of data outputs from the one or more memory banks. Additionally, the memory array comprises one or more write bitlines that share discontinuous metal tracks with one or more read bitlines.