The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 1998
Filed:
Mar. 06, 1997
Adrianus W Ludikhuize, Eindhoven, NL;
Maarten J Van Dort, Nijmegen, NL;
U.S. Philips Corporation, New York, NY (US);
Abstract
A deep diffusion of the back-gate region provided in a self-aligned manner with respect to the gate electrode is necessary in a DMOS transistor for obtaining a sufficiently high punch-through voltage between source and drain. The combination of a comparatively heavy back-gate implantation and a light source implantation and a heavy source implantation with spacer on the gate electrode, and the use of interstitial diffusion and accelerated diffusion owing to crystal damage render it possible to carry out said diffusion of the back-gate region at a comparatively low temperature, for example below 950 .degree. C. This renders it possible to integrate a DMOST into, for example, standard VLSI CMOS where first .delta.V.sub.th and channel-profile implantations are carried out, and subsequently the poly gates are provided, which means that a diffusion step at a temperature above 1,000 .degree. C. of long duration is no longer allowed. The effect may be enhanced in that the doping of the back-gate region is increased during the p-type LDD implantation of a p-channel MOS and/or the p-type well implantation of an n-channel MOS.