Bitline load and precharge structure for an sram memory

Abstract

An SRAM configures its bitline load structure to implement one of three different precharge schemes, none of which use an ATD circuit. The SRAM monitors its WRITE/READ pin and initiates a first precharging scheme when the SRAM is in a read mode. In the first precharging scheme, every complementary bitline pair is directly coupled to Vcc via a first pmos transistor which is permanently turned on, regardless of whether a memory cell is being read or not. Additionally, both true and false bitlines in every complementary bitline pair are coupled together via a pmos transistor as long as the SRAM remains in a read mode. When in a write mode, the second precharging scheme is initiated causing the second pmos transistor to be turned off and only the first pmos transistors remain active. Thus, all complementary bitline pairs which are not selected for a write operation are pulled up to Vcc by the first pmos transistors. The termination of the write mode activates the third precharging scheme which causes all the bitlines, both true and false, within the memory array to be momentarily shorted together. The cumulative equivalent capacitance of the complementary bitlines pairs which were not selected for a write operation help to pull up the few complementary bitlines pairs which were pull down during the previous write operation.