The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 1998

Filed:

Sep. 29, 1995
Applicant:
Inventors:

Alan Berezin, Austin, TX (US);

Reuben Quintanilla, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06G / ; G06F / ;
U.S. Cl.
CPC ...
364578 ; 395500 ; 364488 ; 364489 ; 364490 ; 364491 ;
Abstract

Method and a system for performing die yield prediction in cooperation with wafer scanning tools. A program analyzes data associated with defects on a wafer substrate, the substrate including multiple layers and multiple die. Files are read that contain defect data for selected layers of the substrate. The defect data includes defect type and defect size information. The defect data is then stacked to identify the layer of first occurrence of each defect and the number, i.e., count, of layers upon which it was redetected. A kill factor is then assigned to each of the defects according to a set of rules, each such rule specifying defect parameters that include layer of first occurrence, redetect count, defect size, and defect type. Failure probabilities, indicative of yield, are then computed for the defects according to the assigned kill factors. The failure probabilites are utilized to calculate the estimated die loss for selected wafers by layer and defect type.


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