The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 1998

Filed:

Dec. 31, 1996
Applicant:
Inventors:

Harold L Massie, West Linn, OR (US);

G Mark Johnston, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F / ;
U.S. Cl.
CPC ...
323282 ;
Abstract

A DC-DC voltage conversion provides a voltage to a processor in a mobile computer system using a high side power FET and a low side power FET, each having a variable gate discharge time dependent on the applied battery voltage. The power FETs are arranged in a synchronous totem pole configuration with a junction point therebetween, coupled between a voltage input terminal and ground, with the junction point coupled to a voltage output terminal. Each of the power FETs is driven by a FET driver, with the driver being coupled to the output of a comparator comparing a reference voltage with the output voltage. To avoid cross-conduction, the high side power FET and the low side power FET are coupled to each other in such a manner that the event of one turning off will turn on the other after a dead time determined by the threshold sense circuit, plus delays of the devices used in the embodiment.


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