The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 1998

Filed:

Sep. 25, 1996
Applicant:
Inventor:

Srinivasan Murari, Fremont, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ; G06F / ;
U.S. Cl.
CPC ...
395500 ; 395376 ; 395379 ; 395385 ;
Abstract

A method and apparatus for emulating status flags on a computer system that has no native support for status flags. One embodiment of the invention includes decoding an arithmetic instruction executable on a first Instruction Set Architecture (ISA), wherein the instructions generates at least one status flag when executed on the first ISA. The arithmetic instruction is translated to be executable on a second ISA. When executed on the second ISA, the translated arithmetic instruction generates a first intermediate result by performing a first logical exclusive-or (XOR) operation between a first operand and a second operand. The arithmetic instruction then generates a first final result by performing a second XOR operation between the first intermediate result and an arithmetic result, which was generated by an arithmetic operation specified by the arithmetic instruction. As a result, the first final result has at least one bit representing a status flag of the arithmetic result.


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