Product wafer yield prediction method employing a unit cell approach

Abstract

A method is presented for determining a predicted yield value for a silicon wafer subjected to a wafer fabrication process. The wafer fabrication process forms multiple integrated circuits (i.e., chips) upon a surface of the wafer. A unit cell region is chosen on the surface of the wafer and within the boundaries of a single chip. Two or more masking steps which form features within the selected unit cell region are chosen as critical masking steps. Portions of the unit cell region within which a given critical masking step forms features with minimum dimensions or spacings are identified as critical regions. A fraction of the unit cell region enveloped by critical regions is used to compute a critical chip area A' for the critical masking step. An electrical fault density D' is computed for each critical masking step as a product of an expected total defect density D.sub.t and a fraction of defects expected to result in catastrophic failures f.sub.c. An estimated yield value is calculated for each critical masking step by substituting A' and D' for A and D, respectively, in a yield equation associated with an existing yield prediction model. A predicted yield Y' for the silicon wafer is computed as the product of the estimated yield values of the critical masking steps.