Method and apparatus for servicing a plurality of fifo's in a capture

Abstract

The present invention provides a direct memory access unit for use in prioritizing the servicing of FIFO buffers in a capture gate array coupled to a video processing device. The capture gate array comprises at least a FIFO input unit having a plurality of FIFO buffers for receiving as input to the capture gate array separated Y, U and V bitmap data entries and a bus interface unit coupled to a video memory bus for outputting the data entries to the video processing device. The direct memory access unit preferably comprises at least a signal generation unit, a logic unit and a control unit. The signal generation unit receives as input from the FIFO unit depth values for the FIFO buffers representing the number of data entries currently stored in respective FIFO buffers in addition to comparators which compare the depth value of each FIFO buffer with at least first and second trip point values stored in at least first and second buffers. The trip point values represent predetermined numbers of data entries within the FIFO buffers, and the second trip point value is set so as to be greater in magnitude than the first trip point value. The signal generation unit then generates a first trip point signal for each FIFO buffer having a depth value equal to or greater than the first trip point value but less than the second trip point value and a second trip point signal for each FIFO buffer having a depth value equal to or greater than the second trip point value. The logic unit is coupled to the signal generation unit and comprises combinational logic for prioritizing the generated trip point signals associated with the respective FIFO buffers. The logic unit further generates FIFO service requests in accordance with the prioritized trip point signals.