Optimizing hardware and software co-simulator

Abstract

An optimizing hardware-software co-simulator is constituted with a logic simulator, a number of bus interface models, a number of memory models, a number of instruction set simulators, and a co-simulation optimization manager for co-simulating a hardware-software system having memory. Co-simulation is performed with a single coherent view of the memory of the hardware-software system, transparently maintained by the co-simulation optimization manager for both the hardware and software simulations. This single coherent view includes at least one segment of the memory being viewed as configured for having selected portions of the segment to be statically or dynamically configured/reconfigured for either unoptimized or optimized accesses, wherein unoptimized accesses are performed through hardware simulation, and optimized accesses are performed 'directly' by the co-simulation optimization manager, by-passing hardware simulation. Co-simulation of a hardware-software system is performed with or without the co-simulation optimization manager optimizing simulation time, which is statically or dynamically configured/reconfigured, and optionally in accordance to a desired clock cycle ratio between hardware and software simulations, also statically or dynamically configured/reconfigured.