The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 1998
Filed:
Sep. 17, 1996
George J Gadelkarim, Pleasanton, CA (US);
Ted Vucurevich, San Jose, CA (US);
William H Kao, Saratoga, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method for generating a physical integrated circuit layout, using the similarity between a template and the physical layout as a metric. This automated template-driven layout methodology creates a physical integrated circuit layout which approximates the specified template as closely as practicably possible. The similarity of the positioning of circuit elements in a physical layout is improved with regard to the positioning of those same circuit elements in a template. The circuit elements' placement is incrementally improved by attaching a cost to each placement, with a lower cost reflecting a better match between circuit element placement in the physical layout and the template. Fuzzy logic concepts are employed to determine the cost of a given layout.