The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 1998
Filed:
May. 22, 1995
Larry Louis Moresco, San Carlos, CA (US);
Richard L Wheeler, San Jose, CA (US);
Solomon I Beilin, San Carlos, CA (US);
David A Horine, Los Altos, CA (US);
Fujitsu Limited, , JP;
Abstract
A power distribution structure for a multichip module and a method for fabricating the same are shown. According to the method of the present invention, a base plate is provided, a plurality of mesas arranged in a pattern are formed on the base plate, the mesas having electrically conductive upper surfaces which lie substantially in a single plane. A thin, conformal dielectric layer is then formed over the exposed surfaces of the mesas and the support base and a conductive material is deposited over the dielectric material filling the area between and surrounding the mesas. The resulting structure is then planarized, as by polishing, such that the upper surfaces of the mesas and the upper surface of the conductive material surrounding the mesas lie in substantially one plane and are electrically isolated from each other by the dielectric material. A multilayered thin film structure for a multichip module may then be formed over the power distribution structure and power and ground potentials supplied to microelectronic components, such as integrated circuit chips, mounted on the surface of the thin film structure using vias routed through the thin film structure.