The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 1998
Filed:
Sep. 04, 1996
Tetsu Nagamatsu, Kawasaki, JP;
Tadahiro Kuroda, Yokohama, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
The comparator circuit comprises a first comparator circuit having a differential input stage composed of P-channel FETs; a second comparator circuit having a differential input stage composed of N-channel FETs; pull-up and pull-down resistances connected to the output terminals of the two comparator circuits, respectively; at least one skew adjusting circuit having a delay circuit and a selector; and a logical gate for obtaining the two output signals of the two comparator circuits. Since the two differential input signals can be received by the two comparator circuits and according to the potentials of the two differential input signals, even if the supply potential is low, the comparator circuit can compare the two differential input signals in a wide potential range from the ground potential and the supply potential, so that it is possible to provide a high speed interface circuit which can satisfy the LVDS standard at a low supply potential.