Cell topology for power transistors with increased packing density

Abstract

The present invention discloses a power transistor cell supported on a semiconductor substrate with a top surface and a bottom surface. The power transistor cell includes a drain region, doped with impurities of a first conductivity type, formed at the bottom surface. The power transistor cell further includes a polysilicon gate layer overlaying the top surface includes a polysilicon opening disposed substantially in a central portion of the transistor cell with a remaining portion of the polysilicon layer constituting a gate and defining an outer boundary for the transistor cell wherein the polysilicon opening and the outer boundary defined by the gate for the transistor cell constituting substantially non-orthogonal parallelograms. The power transistor further includes a source region, doped with the first conductivity type, disposed in the substrate underneath and around an outer edge of the source opening with a small portion extends underneath the gate. The power transistor further includes a body region, doped with a second conductivity type, disposed in the substrate surrounding the source region and an entire portion of the substrate underneath the polysilicon opening having a small portion extends underneath the gate near the cell boundary. The packing density of the transistor cell is improved with the parallelogram cell occupies less areas than the regular square cell having the same total channel width.