Multi-bank memory system and method having addresses switched between

Abstract

A memory subsystem with multiple memory banks each having an array of memory cells includes address control circuitry for presenting address bits to the row and column decoders of the memory banks and switching the row and column addresses presented to the different banks. Address control circuitry may be a translation look ahead buffer or may include an address translator, a row address buffer, and a column address buffer. The memory subsystem may also include input/output circuitry for inputting address bits in response to row address strobe and column address strobe signals. Input/output circuitry may allow both serial and parallel access to the multiple memory banks. A method for accessing the memory subsystem includes addressing a row in the array of a first memory bank using a first set of address bits, addressing a column in the array of the first memory bank using a second set of address bits, accessing a cell at the intersection of the selected row and selected column in the first memory bank, addressing a row in the array of a second memory bank using the second set of address bits, addressing a column in the array of the second memory bank using the first set of address bits, accessing a cell at the intersection of the selected row and selected column in the second memory bank.