Data in/out channel control circuit of semiconductor memory device

Abstract

A data in/out channel control circuit for a semiconductor memory device with multi-bank structure includes a plurality of split banks each provided with memory cell arrays, each split bank having a plurality of bit line pairs and a sub in/out line pair connected through a column selection transistor pair, for efficiently connecting data from the bit line pairs to a global in/out line pair. The circuit enables transmission of only the data in a given block bank through the global in/out line pair and the sub in/out line pairs with bank selection information and block selection information. The circuit includes a pair of global in/out lines, global column selection lines extending in a direction of the bit line pair, a column decoding means for activation of any one of the global column selection lines responsive to a decoding of the column selection information, local column selection lines connected to each gate of the column selection transistors, means for generating a bank selection signal for selecting at least one of the plurality of banks by decoding column selection information and row selection information, and a switching means for connecting the sub in/out line pair of the corresponding bank to the global in/out line pair as well as connecting the global column selection line to the local column selection line of the bank in response to the bank selection signal.