The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 1998

Filed:

Oct. 16, 1996
Applicant:
Inventors:

Megumi Suzuki, Kariya, JP;

Akiyoshi Asai, Kariya, JP;

Jun Sakakibara, Kariya, JP;

Assignee:

Denso Corporataion, Kariya, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
257357 ; 257352 ; 257355 ; 257356 ; 257359 ; 257360 ;
Abstract

In a semiconductor integrated circuit device having an input protection circuit element such as a diode formed in the semiconductor substrate, the leak current is suppressed. An nMOS transistor and a pMOS transistor that constitute a CMOS inverter circuit are formed using a SOI structure. An n-type diffusion layer and p-type diffusion layer are formed within the semiconductor substrate to thereby construct a protective diode that forms an input protection circuit for the CMOS inverter circuit. By surrounding the outer periphery of the n-type diffusion layer with the p-type diffusion layer, the depletion layer that is formed at an interface between the semiconductor substrate and a buried insulation film therein is cut off by the p-type diffusion layer, thereby suppressing the leak current between the n-type diffusion layer and the p-type diffusion layer.


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