Analog channel for mixed-signal-vlsi tester

Abstract

Mixed-signal tester architecture and methods are provided which minimize transfer of data, offer parallel data post-processing within the analog channels, and allow flexible synchronization. Multiple analog channels each have a source digital signal processor (DSP), a digital source sequencer, digital source instrumentation, analog source instrumentation, analog measure instrumentation, digital measure instrumentation, a digital pin multiplexer, a digital measure sequencer, DSP-addressable multi-bank capture memory, a capture digital signal processor, and an inter-DSP feedback path for communication between the source DSP and the capture DSP. Each analog channel can be arranged in a feedback loop through either its analog and/or digital instrumentation using the inter-DSP feedback path. DUT response is processed in the channel, the result is used to define parameters for a subsequent test cycle, and a signal corresponding to these parameters is generated and applied to the DUT. This loop-back of the result of a test cycle within the analog channel to define the next test cycle speeds up the test process. The source DSP can synthesize signals in real time and apply these to the DUT through analog or digital source instrumentation, and can synthesize source sequencer memory addresses (pointers to waveform-data stored in memory which represent waveforms or waveform segments) in real time and apply these signals to the DUT through analog or digital source instrumentation. DUT response is written to capture-memory in the channel which is directly addressable by the capture DSP, avoiding transfer of data before processing and further speeding the test process. Multi-bank capture memory controlled by the capture DSP allows data representing DUT response to be written into one bank while previously-written data in another bank is processed. This interleaving of data capture and data processing allows simultaneous capture and processing, further speeding the test process.