The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 1998
Filed:
Jul. 17, 1995
Greg A Peek, Beaverton, OR (US);
Craig D Cedros, Beaverton, OR (US);
Dick Reohr, Jr, Aloha, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An apparatus for interfacing a memory with a bus in a computer system is described. The memory has a data path width which is different than the data path width of the bus. The apparatus comprises a first and a second buffer, a first and a second address generation circuit, and a control circuit. The first buffer is for storing a first portion and a second portion of a first data read from the memory during a read operation which are to be sent to the bus in parallel. The first address generation circuit is for receiving a first address from the bus during the read operation and generating a first memory address to address the memory for the first portion of the first data and a second memory address to address the memory for the second portion of the first data. The second buffer circuit is for storing a second data received from the bus during a write operation. The second address generation circuit is for receiving a second address from the bus for writing the second data into the memory during the write operation, and for generating a third memory address to write a third portion of the second data to the memory and a fourth memory address to write a fourth portion of the second data to the memory. During the read operation, the control circuit causes (1) the first address generation circuit to generate the first memory address and the first buffer to receive the first portion of the first data, and then (2) the first address generation circuit to generate the second memory address and the first buffer to receive the second portion of the first data. During the write operation, the control circuit causes (3) the second address generation circuit to generate the third memory address and the second buffer to send the third portion of the second data, and then (4) the second address generation circuit to generate the fourth memory address and the second buffer to send the fourth portion of the second data.