The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 1998
Filed:
Jan. 08, 1997
Shiuh-Hui Steven Chen, Lake Zurich, IL (US);
Carl Ross, Mundelin, IL (US);
Donald L Hughes, Mesa, AZ (US);
Motorola Inc., Schaumburg, IL (US);
Abstract
A capacitive pressure sensor and method of fabricating the sensor includes providing a layered structure including a second silicon layer (115), a second insulating layer (203, 205) in contact with the second silicon layer (115), a first silicon layer (123) in contact with the second insulating layer (203, 205), a first insulating layer (201) in contact with the first silicon layer (123), and a mask layer (221) in contact with the first insulating layer (201). A major exposed surface (220) of the second silicon layer (115) is provided by mechanically reducing a thickness (210) of the second silicon layer (115) to a predetermined thickness (116). Preferably this is done by grinding and then polishing the second silicon layer (115). In one embodiment a third insulating layer (211) is in contact with the second major surface (220) of the second silicon layer (115). A third silicon layer (101) having a fourth insulating layer (109) forming a perimeter structure (215) positioned above and surrounding a predefined area (114) of the third silicon layer (101). The perimeter structure (215) is bonded to the third insulating layer (211), wherein a chamber (113) is formed between the third insulating layer (211), the perimeter structure (215), and the predefined area (114). Preferably, a portion of the first silicon layer (123) is removed using an anisotropic etch step.