The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 1998
Filed:
Jan. 17, 1996
Hiroaki Onishi, Higashiosaka, JP;
Haruto Nagata, Sakai, JP;
Masato Hirano, Osaka, JP;
Kenichiro Suetsugu, Nishinomiya, JP;
Matsushita Electric Industrial Co., Ltd., Kadoma, JP;
Abstract
A method for mounting on integrated circuit having many leads with narrow pitches on the printed circuit board. In a method, a resist layer is formed between lands on the board, and solder paste is applied with a stencil to the lands so that the positions of the solder paste on the lands are staggered. Then, leads of the integrated circuit are positioned on the lands. Then, reflow soldering of the leads to the lands is performed with the solder paste in a nitrogen environment. In a different embodiment, each land includes a first portion and a second portion having a width narrower than the first portion, and the second portions are arranged staggeredly among the lands. Then, solder paste is applied to the first portions having the wider width. Then, reflow soldering of the leads to the lands is performed with the solder paste in a nitrogen environment. If solder including bismuth is used, reflow soldering can be performed in ambient environment.