The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 1998

Filed:

Jun. 27, 1996
Applicant:
Inventors:

Jashojiban Banik, Aloha, OR (US);

Keng L Wong, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L / ;
U.S. Cl.
CPC ...
327152 ; 327225 ; 327292 ;
Abstract

A method and apparatus for clocking latches in a system having both pulse latches and two-phase latches includes a clock generating circuit for generating a local clock signal based on a global clock signal and also includes a pulse generating circuit for generating a pulse signal based on the global clock signal. A clock signal path transfers the local clock signal from the clock generating circuit to both a first portion and a second portion of the two-phase latch. Similarly, a pulse signal path transfers the pulse signal from the pulse generating circuit to the pulse latch. According to one embodiment, the pulse generating circuit and the clock generating circuit have paths of equal delay, thereby causing a rising edge of the local clock signal to occur at the same time as a rising edge of the pulse signal.


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