Power bus for an integrated circuit including end-to-end arranged

Abstract

An integrated circuit and a process for manufacturing the same wherein the integrated circuit includes a substrate, a first insulative layer disposed on the substrate, and a first conductive layer disposed on the first insulative layer, the first conductive layer having a plurality of conductive channels arranged into horizontal tracks. The plurality of conductive channels are for providing two power sources V.sub.SS and V.sub.CC to cells (e.g. standard cells in control blocks) in the integrated circuit. A second insulative layer is disposed on the first conductive layer, and a second conductive layer is disposed on the second insulative layer, the second conductive layer arranged into a plurality of vertical tracks, each of the plurality of vertical tracks are broken into a plurality of segments. Each of the plurality of segments are for carrying one of the power sources, V.sub.SS and V.sub.CC to the cells in the integrated circuit, each of the plurality of segments coupled to a corresponding channel in the first conductive layer through first vias in the second insulative layer. The integrated circuit may also have a third insulative layer disposed on the second conductive layer, and a third conductive layer disposed on the third insulative layer, the third conductive layer providing interconnection of the segments in each of the vertical tracks through second vias in the third insulative layer, the interconnection provided by horizontal tracks in the third conductive layer. In implemented embodiments, the breaking of the vertical power tracks in the second conductive layer into segments for supplying power to the cells results in a net decrease in the area consumed by power buses in the cells, and thus, more area is available for non-power signal lines. The overall area of the integrated circuit may be thereby reduced.