The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 1998

Filed:

Nov. 22, 1996
Applicant:
Inventors:

Saied N Tehrani, Tempe, AZ (US);

Jenn-Hwa Huang, Gilbert, AZ (US);

Herbert Goronkin, Tempe, AZ (US);

Ernest Schirmann, Phoenix, AZ (US);

Marino J Martinez, Phoenix, AZ (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257280 ; 257281 ; 257282 ;
Abstract

A stable FET including a substrate structure with a doped layer formed as a portion of the substrate structure and defining an electrically conductive shielding region adjacent a surface of the substrate structure. A channel region is positioned on the shielding region and includes a plurality of epitaxial layers grown on the surface of the substrate structure in overlying relationship to the doped layer. A drain and a source are positioned on the channel region in spaced relationship from each other with a gate positioned in overlying relationship on the channel region between the drain and source. An externally accessible electrical contact is connected to the shielding region and to the source region to provide a path for the removal of internally generated charges, such as holes.


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