The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 1998

Filed:

Dec. 19, 1994
Applicant:
Inventors:

George R Hayek, Cameron Park, CA (US);

Brian K Langendorf, El Dorado Hills, CA (US);

Aniruddha Kundu, Hillsboro, OR (US);

Kuljit S Bains, Folsom, CA (US);

Gary A Solomon, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395308 ; 395306 ;
Abstract

A bridge for coupling a host bus to a peripheral component interconnect (PCI) bus. A controller is used to transfer an address from the host bus while a datapath is used to transfer data from the host bus. The address and data is then transferred to the PCI bus over a set of signal lines coupled to the PCI bus such that each signal line transfers at least a portion of the address as well as at least a portion of data.


Find Patent Forward Citations

Hayek, George. (1998). Low load host/pci bus bridge (U.S. Patent No. 5740385). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5740385

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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